1. Field of the Invention
This invention relates generally to non-volatile memory devices having a floating gate such as an array of flash electrically erasable and programmable read-only memory (EEPROMs) devices. More particularly, the present invention relates to a new and novel method of determining the value of the threshold voltage of a memory core cell in an array of flash EEPROM memory core cells by reading the core cell.
2. Description of the Prior Art
One type of non-volatile memory device is referred to as "flash EEPROMs" which are both programmable and erasable electrically. FIG. 1 illustrates a prior art cross-sectional view of a flash EEPROM cell 10. In these flash memories, a plurality of such one-transistor flash EEPROM cells 10 may be formed on a p-type semiconductor substrate (P-Well) 12 in which each is comprised of an n.sup.+ drain region 14 and an n.sup.+ source region 16 both formed integrally within the substrate. A relatively thin gate dielectric layer 18 is interposed between a top surface of the substrate 12 and a conductive polysilicon floating gate 20. A polysilicon control gate 22 is insulatively supported above the floating gate 20 by a second dielectric layer 24. A channel region 26 in the substrate separates the drain and source regions (14, 16). Further, there are provided terminal pins 28, 30, 32 and 34 for applying a source voltage V.sub.S to the source region 16, a gate voltage V.sub.G to the control gate 22, a drain voltage V.sub.D to the drain region 14, and a well voltage V.sub.W to the substrate 12, respectively.
As is well-known, the charge of the floating gate 20 of the one-transistor cell 10 of FIG. 1 is dependent upon the number of electrons contained in the floating gate. During the programming mode, electrons are added to the floating gate of the cell 10 so as to increase its threshold voltage. The term "threshold" refers to a gate-to-source voltage that must be applied between the gate and the source of the cell in order to cause it to conduct. During the erase mode, electrons are removed from the floating gate of the cell so as to decrease its threshold voltage. In programmed state, the threshold voltage of a cell is typically set at greater than +6.5 volts, while the threshold voltage of a cell in an erased state is typically limited below +3.0 volts.
In order to determine whether the cell has been programmed or not, the cell is read by applying a small positive voltage to the control gate between the +3.0 and +6.5 volt range, typically +5.0 volts, with the source region held at a ground potential (0 volts) and the drain held at a potential between +1 to +2 volts. If the transistor cell conducts or is turned-on, a current will flow through the transistor representing a "1" bit or erased state. On the other hand, if the transistor cell does not conduct or is turned-off no current will flow through the transistor representing a ".0." bit or programmed state.
FIG. 2 is a simplified functional block diagram of a conventional semiconductor integrated memory circuit device 100 which includes a flash EEPROM memory array 102 formed of a plurality of memory core cells MC11-MCnm (each being formed such as the one shown in FIG. 1). The plurality of memory cells MC11-MCnm are arranged in an n.times.m matrix on a single integrated circuit chip. Each of the memory cells is comprised of one of the array core transistors Q.sub.P11 through Q.sub.Pnm which function as a memory transistor for storing data "1" or ".0." therein. Each of the core transistors has its drain connected to one of the plurality of bit lines BL.0.-BLm which are, in turn, connected to a bit line pull-up circuit 104 and a column address decoder 106. All of the sources of the array core transistors are connected to a common array ground potential VSS. Each of the core transistors also has its control gate connected to one of the plurality of word lines WL.0.-WLn which are, in turn, connected to a row address decoder 108.
The row address decoder 108 receives voltage signals from a power supply 110 and distributes the individual voltage signals to the corresponding word lines WL.0.-WLn in response to row address signals A.sub.i received from a state machine 112. At the same time, the bit line pullup circuit 104 receives voltages from the power supply 110 and distributes the individual voltage signals to the corresponding bit lines BL.0.-BLm in response to signals received from the state machine 112. The column decoder 106 provides signals from the various bit lines BL.0.-BLm to sense amplifiers or comparators 114 in response to column address signals A.sub.j received from the state machine 112. Further, the sense amplifiers 114 receive a signal from reference cells of a reference array 116. Responsive to the signals from the column decoder 106 and the reference array 116, the sense amplifiers 114 generate a signal indicating a state of the corresponding bit lines BL.0.-BLm relative to a reference cell line REF which is then passed through data latches 118 to the state machine 112.
In addition, it will be noted that the reference array 116 includes a plurality of reference cells RC1-RCn each being formed by one corresponding reference cell transistor Q.sub.R1 -Q.sub.Rn. The gates of the array core transistors Q.sub.P11 through Q.sub.Pnm and the reference cell transistors Q.sub.R1 -Q.sub.Rn located in the same row are connected to the same word line. For instance, the gates of the transistors Q.sub.P11 -Q.sub.P1m and Q.sub.R1 are all connected to the word line WL.0.. Such semiconductor memory circuit device 100 as described and illustrated thus far is similar to the one in U.S. Pat. No. 5,142,496 to M. A. Van Buskirk entitled "Method for Measuring V.sub.T 'S Less Than Zero Without Applying Negative Voltages," which is hereby incorporated by reference in its entirety.
With reference to FIG. 3 of the drawings, there is shown a simplified schematic circuit diagram of certain portions of the memory circuit device 100 of FIG. 2 to explain how the threshold voltage V.sub.TP of one array core transistor Q.sub.P is measured in the '496 patent of the prior art. In particular, the measuring circuitry 300 of FIG. 3 includes a comparator 120, a reference resistor 122 having a resistance value R.sub.2, a sense ratio resistor 124 having a resistance value R.sub.1 (n.times.R2), a core transistor Q.sub.P and a reference transistor Q.sub.R. The comparator 120 is actually one of the sense amplifiers 114 of FIG. 2.
The reference resistor 122 has its one end connected to a supply potential or voltage VCC, which is typically at +1.0 volts, and its other end connected to the non-inverting input of the comparator 120 at node A. The node A is also connected to the drain of the reference transistor Q.sub.R via the reference cell line REF. One end of the sense ratio resistor 124 is also connected to the supply potential VCC, and the other end thereof is connected to the inverting input of the comparator 120 at node B. The node B is also connected to the drain of the core transistor Q.sub.P via the selected bit line BL. As can be seen, the gates of the core transistor Q.sub.P and the reference transistor Q.sub.R are connected together and receive the same control gate voltage V.sub.g via the selected word line WL. The sense ratio is defined by the number n, where n is typically greater than 1 during the read mode of operation.
In order to measure the threshold voltage V.sub.TP of the core transistor Q.sub.P to determine if it is positive or negative, the comparator 120 is used to effectively compare the threshold voltage V.sub.TP of the core transistor Q.sub.P to the threshold voltage V.sub.TR of the reference transistor Q.sub.R . If the threshold voltage V.sub.TP is less than the threshold voltage V.sub.TR, the comparator 120 will output a logic "1." On the other hand, if the threshold voltage V.sub.TP is greater than the threshold voltage V.sub.TR then the comparator 120 will output a logic "0." However, the actual value of the threshold voltage V.sub.TP in relationship to the value of the threshold voltage V.sub.TR is not straightforward, but must be calculated mathematically by equation (1) in the '496 patent. In other words, the threshold voltage V.sub.TP must be calculated after the word line voltage at which the output of the comparator is changed is known, by inserting the same as well as the sense ratio and the threshold voltage V.sub.TR into the equation (1).
Accordingly, there has been discovered by the inventor a new and novel method of determining the value of the threshold voltage of a memory core cell by simply reading the core cell without requiring any complicated calculations to be performed. The present invention represents a significant improvement over the aforementioned '496 patent of the prior art and as illustrated in FIGS. 2 and 3.